Tinoosh Mohsenin – CAD Design of Digital VLSI Systems I (Grad) – EN.520.691

Paper/Tutorial	Comments
https://www.edaplayground.com	EDA Playground is a free web application that allows users to edit, simulate, and synthesize HDL code.
https://www.youtube.com/watch?v=gExBBwRfu3k	A simple introduction to how EDA Playground works.
https://www.edaplayground.com/x/HjXK	Example Code for a D Flip Flop and Test Bench.
eda_sim_tutorial_edit.mp4	Video Tutorial for Simulation using a Verilog Example and Testbench.
cadence xcelium sim tutorial	Video Tutorial for Cadence Xcelium Simulation using a Flip Flop Example
genus tutorial	Video Tutorial for Genus using Flip Flop Example
copy_template.sh	script to copy template/example project

All future dates tentative until hwk/project assigned.

Number	Due Date	% Hwk/proj grade	Material covered and additional files
1	Sunday, Sept 8th, 11 pm	10%	HW1-ALU.pdf
2	Sunday, September 22nd, 11 pm	15%	HW 2 PDF
3	Phase 1: October 13th, 11:50 pm Phase 2: October 20th	15%	HW3: Convert an RGB image to grayscale image and displaying the post place and route output on monitor Required Materials: HW3 Helpful Materials: RGBtoBW, ImgtoMat, PicturetoMatrix, Design Block Diagram, Parrot, Tutorial for Post Synthesis Simulations
Final Project	Phase 1: Due November 17th 8-bit design Phase 2: Due November 24th 2-bit or binary design Phase 3: Post Synthesis, Layout and Verification of Both designs Due December 3rd Phase 4: Final Report in IEEE 2-Column Conference Paper Format Due December 11th	30%	Design and comparison of a binarized neural network with an 8-bit implementation for a hardware accelerator targeting 10-class handwritten digit recognition using the MNIST dataset. Includes synthesis, post-VLSI layout, and verification. The final report will follow the IEEE two-column format All required files are posted here: Final Project Additional Files: link 1

Future details are tentative.

Date	Lecture	Notes
08/26/2024	lecture01-ASIC.pdf
08/28/2024	Verilog Syntax	Slides with helpful Verilog Syntax from Prof. Paul Jackson at Princeton University
09/02/2024
09/04/2024	Sign Extension	Number representation, sign extension
09/02/2024	Registers, clk, reset	Registers and Clk
09/09/2024	Blocking nonblocking statement	More Verilog Examples, Blocking nonblocking statement
09/11/2024	Fixed-point Number	Fixed point number representation
09/16/2024	Numeric Basics	Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
09/18/2024	Verilog Testing	Overview of Verilog testing and test benches.
09/23/2024	adder/subtractor	Adder/Subtractor, Multiplier
09/25/2024	Registers with Enable and Reset	Modeling Registers with additional Reset or Enable signals
09/30/2024	State Machines	State Machines and example with verilog
10/02/2024	Squaring	Squaring
10/07/2024	Fixed Input Mults	Multipliers
10/09/2024	Memories	Overview of Memories
10/14/2024	Memory and FIFO Examples slides	Memory examples
10/16/2024	Memory and FIFO Examples from book	examples from book
10/21/2024	look up table ROM verilog	Fixed point number reprsentation
10/23/2024	Additional State Machine and memory examples	FSM and memory examples
10/28/2024	comparator sort	comparator, sort example
10/30/2024	ASIC	ASIC design flow
11/04/2024	ASIC Comparison	Slides from Prof. Koushanfar
11/06/2024
11/11/2024
11/13/2024
11/18/2024
11/20/2024
11/25/2024
11/27/2024
12/02/2024
12/04/2024
12/09/2024
12/11/2024
12/16/2024
12/18/2024
12/23/2024
12/30/2024