• Instructor Prof. Tinoosh Mohsenin Barton 309, [email protected]
• Office Hours By Appointment
• Lecture MW 10:30am-11:45am Room : Croft Hall G02
• Teaching Assistant: Uttej K, [email protected]
• Office Hours : Barton 117, Friday 11 AM-12 PM

Course Readings/ Tutorials

Paper/Tutorial	Comments
https://www.edaplayground.com	EDA Playground is a free web application that allows users to edit, simulate, and synthesize HDL code.
https://www.youtube.com/watch?v=gExBBwRfu3k	A simple introduction to how EDA Playground works.
https://www.edaplayground.com/x/HjXK	Example Code for a D Flip Flop and Test Bench.
eda_sim_tutorial_edit.mp4	Video Tutorial for Simulation using a Verilog Example and Testbench.
cadence xcelium sim tutorial	Video Tutorial for Cadence Xcelium Simulation using a Flip Flop Example
genus tutorial	Video Tutorial for Genus using Flip Flop Example
copy_template.sh	script to copy template/example project
Flip Flop example tutorial	Learn how to copy the Flip Flop example to your server
Linux basic commands	Tutorial on Linux basic command which is useful for working with Cadance on server

Homework / Projects

All future dates tentative until HW’s/project assigned.

1	Sunday Sep 7th, 11 59PM	10%	HW1-ALU.pdf
2	Sunday Sep 21th, 11 55 PM	15%	HW2-VLSI.pdf
3 Phase 1	Sunday Oct 4th, 11:55 PM	7.5%	HW3-RGBConverter.pdf Homework Explanation(.mp4) Additional Files: Tutorial for Post Synthesis Simulations (.pdf) RGB to BW code (.m) Image to Matrix code (.py) Picture to Matrix code (.m) Design Block Diagram (picture) Parrot (picture)

Course Topics and Lecture Slides

Future details are tentative.

Date	Lecture	Notes	Logistics
08/25/2025	Introduction slides
08/27/2025	Verilog slides	Slides with helpful Verilog Syntax from Prof. Paul Jackson at Princeton University
09/03/2025	Numeric basics slides	Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
09/08/2025	Registers and Clocks and Resets slides	explaining how Registers and Clocks and Resets work
09/10/2025	Types of statements slides	More Verilog Examples, Blocking nonblocking statement
09/15/2025	Fixed Point slides	Fixed point number representation
09/17/2025	Synthesize TCL VCD_slides Cost_slides Load_slides Library_slides Constraints_slides	Explain different parts of a Synthesize TCL file to understand the commands
09/22/2025	Timing Analysis slides	Overview of Timing Analysis in the digital circuit
09/24/2025	Power Analysis slides	Analysis and Estimation of Power Consumption in VLSI Design
09/29/2025	Registers and Testbench slides	Modeling Registers with additional Reset or Enable signals
10/01/2025	State Machines slides	State Machines and example with Verilog
10/06/2025	Squaring slides	explain Squaring operation
10/08/2025	Other Multipliers slides	Fixed Input Multipliers
10/13/2025	Memories slides	Overview of Memories
10/15/2025	Memories Examples slides	Memory and FIFO examples
10/20/2025	Memory Examples from Book slides	Memory and FIFO examples from the book
10/22/2025	ROM slides	Look up table Rom and Fixed point number representation
10/27/2025	Statemachine with Memory Component slides	FSM and Memories examples
10/29/2025	Comparator slides	Comparator and sort examples
11/03/2025	ASIC slides	ASIC design flow
11/05/2025	Final Project slides	Final Project RISC processor Design
11/10/2025	Instruction Set Review slides	Instruction Sets, RISCs, CISC, Harvard, Von Neumann
11/12/2025	Static Timing slides	Static timing and analysis with an example
11/17/2025	ASIC Floor planning slides	Slides from Prof Riadul Islam
11/19/2025	Innovus slides	Tutorial for Innovus tool
11/24/2025