Tinoosh Mohsenin – CAD Design of Digital VLSI Systems I EN.520.691/520.49 (Spring – 2026)

• Instructor Prof. Tinoosh Mohsenin Barton 309, tinoosh@jhu.edu
• Office Hours By Appointment
• Lecture MW 10:30am-11:45am  Room : Hodson Hall 303
• Teaching Assistant: Mozhgan Navardi, mnavard1@jhu.edu
• Office Hours : Barton 117, Friday 11 AM-12 PM

Course Readings/ Tutorials

Paper/Tutorial	Comments
https://www.edaplayground.com	EDA Playground is a free web application that allows users to edit, simulate, and synthesize HDL code.
https://www.youtube.com/watch?v=gExBBwRfu3k	A simple introduction to how EDA Playground works.
https://www.edaplayground.com/x/HjXK	Example Code for a D Flip Flop and Test Bench.
eda_sim_tutorial_edit.mp4	Video Tutorial for Simulation using a Verilog Example and Testbench.
cadence xcelium sim tutorial	Video Tutorial for Cadence Xcelium Simulation using a Flip Flop Example
genus tutorial	Video Tutorial for Genus using Flip Flop Example
copy_template.sh	script to copy template/example project
Flip Flop example tutorial	Learn how to copy the Flip Flop example to your server
Linux basic commands	Tutorial on Linux basic command which is useful for working with Cadance on server
pnr_steps_updated-no block.pdf pnr_flow_slides.pdf	Tutorial on place and route

Homework / Projects

All future dates tentative until HW’s/project assigned.

Course Topics and Lecture Slides

Future details are tentative.

Date	Lecture	Notes	Logistics
01/21/2026	Introduction slides
01/26/2026	Verilog slides	Slides with helpful Verilog Syntax from Prof. Paul Jackson at Princeton University
01/28/2026	1. Sign slides 2. Fixed Point slides 3. Types of statements slides	1. Number representation and sign extension 2. Fixed point number representation. 3. More Verilog Examples, Blocking nonblocking statement
02/02/2026	Registers and Clocks and Resets slides	Explaining how Registers and Clocks and Resets work
02/11/2026	Numeric basics slides	Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
02/13/2025	Synthesize TCL VCD_slides Cost_slides Load_slides Library_slides Constraints_slides	Explain different parts of a Synthesize TCL file to understand the commands
02/16/2026	Timing Analysis slides	Overview of Timing Analysis in the digital circuit
02/16/2026	Power Analysis slides	Analysis and Estimation of Power Consumption in VLSI Design
02/18/2026	Registers and Testbench slides	Modeling Registers with additional Reset or Enable signals
02/18/2026	State Machines slides	State Machines and example with Verilog
02/23/2026	Squaring slides	explain Squaring operation
02/23/2026	Other Multipliers slides	Fixed Input Multipliers
02/25/2026	Memories slides	Overview of Memories
02/25/2026	Memories Examples slides	Memory and FIFO examples
03/02/2026	Memory Examples from Book slides	Memory and FIFO examples from the book
03/02/2026	ROM slides	Look up table Rom and Fixed point number representation
03/02/2026	Statemachine with Memory Component slides	FSM and Memories examples
03/04/2026	Comparator slides	Comparator and sort examples
03/09/2026	ASIC slides	ASIC design flow
03/11/206	Place and Route pnr_flow_slides.pdf pnr_steps_updated-no block.pdf	Tutorial on place and route
03/23/2026	Final Project slides	Final Project RISC processor Design
03/25/2026	Instruction Set Review slides	Instruction Sets, RISCs, CISC, Harvard, Von Neumann
	Static Timing slides	Static timing and analysis with an example
	ASIC Floor planning slides	Slides from Prof Riadul Islam
	Innovus slides	Tutorial for Innovus tool