- Instructor Prof. Tinoosh Mohsenin Barton 309, Tinoosh(AT)jhu.edu
- Office hours By appointment
- Lecture M-W 10:30am-11:45am Room : Maryland 217
- There is no TA for this class, Please refer to our Piazza discussion forum for questions.
Course Readings/ Tutorials
| Paper/Tutorial | Comments |
| Downloading and Installing Vivado | Instructions to Install Vivado |
| User manual for the Nexys-4 Artix FPGA board | |
| Pin locations for Artix and Nexys board | |
| Verilog example files Eight_Bit_Multiplier.v , Eight_Bit_Multiplier_t | |
| Full Adder and testbench | Example of a 2-bit fulladder, instantiation in top and testbench in verilog. Adder and instantiation tutorial |
| Xilinx Vivado multiple labs | Very helpful link for different labs in Vivado. |
| Additional resources for Verilog and Digital Design | Advanced Digital Design: Prof. Koushanfar at UCSD |
Homework / Projects
All future dates tentative until hwk/project assigned.
| Number | Due Date | % Hwk/proj grade | Material covered and addiotional files |
| 1 | Sunday, Sept 3rd,11 pm | No grade | learn the fundamental components of the Xilinx FPGA tools required to enter and assemble submodules to a top module code and demonstrate on FPGA Nexys4 board manual verilog file blinky.v xdc file timing.xdc Video for demonstration of Tutorial, Video for demonstration of Assignment |
| 2 | Phase1 Testbench simulation and demo Sept 10th, Phase 2 Hardware demo in class submission Sunday Sept 24th, 11pm | 7.5% | Arithmetic logic, image color change and VGA. Required files, read me to use python, VGA description, Youtube VGA by Simply Embedded, Design Block Diagram |
| 3 | Sunday Oct 8th, 11 pm | 7.5% | Synthesis and place and route, timing constraints, State Machines, FIFO and Memory design in a system, simulation only. |
| 4 | Phase 1: Sunday, Oct 15, Phase 2: Sunday Oct22nd, Phase 3: Sunday, Oct 29th, Phase 4 and final VGA demo: Sunday, Nov 5th. | 15% | Two layer Convolution neural network design with maxpooling for Edge Detection, FPGA hardware, latency and power analysis, VGA demo Helpful Material: Link 1, Link 2, Link 3 |
| Final Project | Phase 1: Sunday, Nov 26, Phase 2: Sunday Nov 26, Phase 3: Sunday, Dec 3rd, Phase 4 Sunday Dec 10th Final Demo and Presentation December 13 9:30 to 12 pm. | MNIST, 10 class handwritten digit recognition on FPGA. Implementation of a 2 layer fully connected with Relu activation on FPGA. FPGA hardware, latency and power analysis, Seven Segment and VGA demo All required files are posted: here. Final project Helpful Material: link1, Link 2 |
Course Topics and Lecture Slides
Future details are tentative.
| Date | Lecture | Topics |
| 08/28/2023 | Lecture 1 | Course introduction, Syllabus |
| 08/30/2023 | Verilog Syntax | Slides with helpful Verilog Syntax from Prof. Paul Jackson at Princeton University |
| 09/06/2023 | Artix FPGA, Verilog Module and examples | Artix FPGA, Verilog Module and examples |
| 09/11/2023 | Sign Extension | Number representation, sign extension |
| 09/11/2023 | Registers, clk, reset | Registers and Clk |
| 09/11/2023 | Blocking nonblocking statement | More Verilog Examples, Blocking nonblocking statement |
| 09/13/2023 | Fixed-point Number | Fixed point number representation |
| 09/13/2023 | Numeric Basics | Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder) |
| 09/13/2023 | Verilog Testing | Overview of Verilog testing and test benches. |
| 09/13/2023 | adder/subtractor | Adder/Subtractor, Multiplier |
| 09/18/2023 | Registers with Enable and Reset | Modeling Registers with additional Reset or Enable signals |
| 09/18/2023 | Sequential Basics, Registers and Pipelining | Overview of Sequential Logic & Pipelining and example |
| 09/18/2023 | Pipelining & Latency | Pipelining & Latency |
| 09/20/2023 | State Machines | State Machines and example with verilog |
| 09/20/2023 | Squaring | Squaring |
| 09/20/2023 | Fixed Input Mults | Multipliers |
| 09/20/2023 | Memories | Overview of Memories |
| 09/27/2023 | Memory and FIFO Examples slides | Memory examples |
| 09/27/2023 | Memory and FIFO Examples from book | examples from book |
| 09/27/2023 | look up table ROM verilog | Fixed point number reprsentation |
| 10/02/2023 | Additional State Machine and memory examples | FSM and memory examples |
| 10/04/2023 | comparator sort | comparator, sort example |
| 10/09/2023 | FPGAs 1 | FPGAs structures, FPGA vs ASIC design flow |
| 10/11/2023 | FPGAs vs. ASIC Comparison | Slides from Prof. Koushanfar |
| 10/16/2023 | Xilinx Vivado Timing | Timing Optimization and Analysis Document |
| 10/18/2023 | Xilinx Video Vivado Timing | Xilinx Vivado Video on Timing |
| 10/23/2023 | Vivado power Analyzer | Overview of Power Analysis and Optimization. |
| 10/23/2023 | Xilinx Video Vivado power Analyzer | Overview of Power Analysis and Optimization. |
| 10/30/2023 | Switch between LUT and DSP implementation | lookup table or ROM verilog,readmemh |
| 10/30/2023 | Vivado Timing Constraints | Timing Constraints |
| 10/30/2023 | Vivado Power Consumption | Power Consumption |
| 11/01/2023 | HW4 Final Presentation and Demo | |
| 11/06/2023 | Midterm Practice and Quiz | |
| 11/13/2023 | Midterm | |
| 11/15/2023 | Final Project Discussion | |
| 11/25/2023 | Packed/Unpacked Array, Memory Modeling | Slides from from Prof. Koushanfar at UCSD |