• Instructor Prof. Tinoosh Mohsenin Barton 309, Tinoosh(AT)jhu.edu
  • Office hours By appointment
  • Lecture M-W 10:30am-11:45am Room : Maryland 217
  • There is no TA for this class, Please refer to our Piazza discussion forum for questions.

Course Readings/ Tutorials

Downloading and Installing Vivado
Instructions to Install Vivado
User manual for the Nexys-4 Artix FPGA board
Pin locations for Artix and Nexys board
Verilog example files Eight_Bit_Multiplier.v , Eight_Bit_Multiplier_t
Full Adder and testbench
Example of a 2-bit fulladder, instantiation in top and testbench in verilog. Adder and instantiation tutorial
Xilinx Vivado multiple labs
Very helpful link for different labs in Vivado.
Additional resources for Verilog and Digital Design
Advanced Digital Design: Prof. Koushanfar at UCSD

Homework / Projects

All future dates tentative until hwk/project assigned.

NumberDue Date% Hwk/proj gradeMaterial covered and addiotional files
 1  Sunday, Sept 3rd,11 pm No gradelearn the fundamental components of the Xilinx FPGA tools required to enter and assemble submodules to a top module code and demonstrate on FPGA Nexys4 board manual verilog file blinky.v xdc file timing.xdc Video for demonstration of Tutorial, Video for demonstration of Assignment
 2 Phase1 Testbench simulation and demo Sept 10th, Phase 2 Hardware demo in class submission Sunday Sept 24th, 11pm7.5%Arithmetic logic, image color change and VGA. Required files, read me to use python, VGA description, Youtube VGA by Simply Embedded, Design Block Diagram
 3Sunday Oct 8th, 11 pm7.5%Synthesis and place and route, timing constraints, State Machines, FIFO and Memory design in a system, simulation only.
 4Phase 1: Sunday, Oct 15, Phase 2: Sunday Oct22nd, Phase 3: Sunday, Oct 29th, Phase 4 and final VGA demo: Sunday, Nov 5th. 15%Two layer Convolution neural network design with maxpooling for Edge Detection, FPGA hardware, latency and power analysis, VGA demo

Helpful Material: Link 1, Link 2, Link 3
 Final ProjectPhase 1: Sunday, Nov 26, Phase 2: Sunday Nov 26, Phase 3: Sunday, Dec 3rd, Phase 4 Sunday Dec 10th
Final Demo and Presentation December 13 9:30 to 12 pm.
MNIST, 10 class handwritten digit recognition on FPGA. Implementation of a 2 layer fully connected with Relu activation on FPGA. FPGA hardware, latency and power analysis, Seven Segment and VGA demo
All required files are posted: here. Final project
Helpful Material: link1, Link 2

Course Topics and Lecture Slides

Future details are tentative.

08/28/2023Lecture 1Course introduction, Syllabus
08/30/2023Verilog SyntaxSlides with helpful Verilog Syntax from Prof. Paul Jackson at Princeton University
09/06/2023Artix FPGA, Verilog Module and examplesArtix FPGA, Verilog Module and examples
09/11/2023Sign ExtensionNumber representation, sign extension
09/11/2023Registers, clk, resetRegisters and Clk
09/11/2023Blocking nonblocking statementMore Verilog Examples, Blocking nonblocking statement
09/13/2023Fixed-point NumberFixed point number representation
09/13/2023Numeric BasicsSlides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder)
09/13/2023Verilog TestingOverview of Verilog testing and test benches.
09/13/2023 adder/subtractor Adder/Subtractor, Multiplier
09/18/2023Registers with Enable and ResetModeling Registers with additional Reset or Enable signals
09/18/2023Sequential Basics, Registers and PipeliningOverview of Sequential Logic & Pipelining and example
09/18/2023Pipelining & LatencyPipelining & Latency
09/20/2023State MachinesState Machines and example with verilog
09/20/2023Fixed Input MultsMultipliers
09/20/2023MemoriesOverview of Memories
09/27/2023Memory and FIFO Examples slidesMemory examples
09/27/2023Memory and FIFO Examples from bookexamples from book
09/27/2023look up table ROM verilogFixed point number reprsentation
10/02/2023Additional State Machine and memory examplesFSM and memory examples
10/04/2023comparator sortcomparator, sort example
10/09/2023FPGAs 1FPGAs structures, FPGA vs ASIC design flow
10/11/2023FPGAs vs. ASIC ComparisonSlides from Prof. Koushanfar
10/16/2023Xilinx Vivado TimingTiming Optimization and Analysis Document
10/18/2023Xilinx Video Vivado TimingXilinx Vivado Video on Timing
10/23/2023Vivado power AnalyzerOverview of Power Analysis and Optimization.
10/23/2023Xilinx Video Vivado power AnalyzerOverview of Power Analysis and Optimization.
10/30/2023Switch between LUT and DSP implementationlookup table or ROM verilog,readmemh
10/30/2023Vivado Timing ConstraintsTiming Constraints
10/30/2023Vivado Power ConsumptionPower Consumption
11/01/2023HW4 Final Presentation and Demo
11/06/2023Midterm Practice and Quiz
11/15/2023Final Project Discussion
11/25/2023Packed/Unpacked Array, Memory Modeling Slides from from Prof. Koushanfar at UCSD