- Instructor Prof. Tinoosh Mohsenin Barton 309, [email protected]
- Office Hours By Appointment
- Lecture TTh 10:30am-11:45am Room : Krieger Hall 302
- Teaching Assistant: Arman Hatami, [email protected]
- Office Hours By Appointment
Course Readings/ Tutorials
| Paper/Tutorial | Comments |
| https://www.edaplayground.com | EDA Playground is a free web application that allows users to edit, simulate, and synthesize HDL code. |
| https://www.youtube.com/watch?v=gExBBwRfu3k | A simple introduction to how EDA Playground works. |
| https://www.edaplayground.com/x/HjXK | Example Code for a D Flip Flop and Test Bench. |
| eda_sim_tutorial_edit.mp4 | Video Tutorial for Simulation using a Verilog Example and Testbench. |
| cadence xcelium sim tutorial | Video Tutorial for Cadence Xcelium Simulation using a Flip Flop Example |
| genus tutorial | Video Tutorial for Genus using Flip Flop Example |
| copy_template.sh | script to copy template/example project |
| Flip Flop example tutorial | Learn how to copy the Flip Flop example to your server |
| Linux basic commands | Tutorial on Linux basic command which is useful for working with Cadance on server |
Homework / Projects
All future dates tentative until HW’s/project assigned.
| Number | Due Date | % Homework/Project grade | Material covered and additional files |
| 1 | Wednesday, Jan 29th | 10% | HW1-ALU.pdf |
| 2 | Sunday, Feb 16th | 15% | HW2-VLSI.pdf |
| 3 phase 1 | Sunday,Mar 2nd EXT to Thursday, Mar 6th | 7.5% | HW3-RGBConverter.pdf Homework Explanation(.mp4) Additional Files: Tutorial for Post Synthesis Simulations (.pdf) RGB to BW code (.m) Image to Matrix code (.py) Picture to Matrix code (.m) Design Block Diagram (picture) Parrot (picture) |
| 3 phase 2 | Monday,Mar 10th | 7.5% | Same files as phase 1 + Place and Route instructions (.pdf) + Place and Route Video Tutorial (.mp4) |
| 3 phase 3 | Monday,Mar 24th | 10% | Same as phase 1 and 2 |
| Final Project |
Course Topics and Lecture Slides
Future details are tentative.
| Date | Lecture | Notes | Logistics |
| 01/21/2025 | Introduction slides | ||
| 01/23/2025 | Verilog slides | Slides with helpful Verilog Syntax from Prof. Paul Jackson at Princeton University | |
| 01/28/2025 | Sign slides | Number representation and sign extension | |
| 01/30/2025 | Registers and Clocks and Resets slides | explaining how Registers and Clocks and Resets work | |
| 02/04/2025 | Types of statements slides | More Verilog Examples, Blocking nonblocking statement | |
| 02/06/2025 | Fixed Point slides | Fixed point number representation | |
| 02/11/2025 | Numeric basics slides | Slides from reference book along with Verilog examples (covers numeric basics, Adders, Multi-input adder) | |
| 02/13/2025 | Synthesize TCL VCD_slides Cost_slides Load_slides Library_slides Constraints_slides | Explain different parts of a Synthesize TCL file to understand the commands | |
| 02/18/2025 | Timing Analysis slides | Overview of Timing Analysis in the digital circuit | |
| 02/20/2025 | Power Analysis slides | Analysis and Estimation of Power Consumption in VLSI Design | |
| 02/25/2025 | Registers plus slides | Modeling Registers with additional Reset or Enable signals | |
| 02/27/2025 | State Machines slides | State Machines and example with Verilog | |
| 03/04/2025 | Squaring slides | explain Squaring operation | |
| 03/06/2025 | Multipliers Plus slides | Fixed Input Multipliers | |
| 03/11/2025 | Memories slides | Overview of Memories | |
| 03/13/2025 | Memories Plus slides | Memory and FIFO examples | |
| 03/25/2025 | Memories Plus Plus slides | Memory and FIFO examples from the book | |
| 03/27/2025 | ROM slides | Look up table Rom and Fixed point number representation | |
| 04/01/2025 | State Machines Plus slides | FSM and Memories examples | |
| 04/03/2025 | Comparator slides | Comparator and sort examples | |
| 04/08/2025 | ASIC slides | ASIC design flow | |
| 04/10/2025 | ASIC Plus slides | Slides from Prof. Koushanfar about ASIC comparison | |
| 04/10/2025 | |||
| 04/15/2025 | |||
| 04/17/2025 | |||
| 04/22/2025 | |||
| 04/24/2025 |